US 12,230,349 B2
Imprint management for memory
Shashank Bangalore Lakshman, Boise, ID (US); Jonathan D. Harms, Meridian, ID (US); Jonathan J. Strand, Boise, ID (US); and Sukneet Singh Basuta, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 31, 2023, as Appl. No. 18/129,585.
Application 18/129,585 is a division of application No. 17/399,872, filed on Aug. 11, 2021, granted, now 11,631,473.
Application 17/399,872 is a division of application No. 16/580,935, filed on Sep. 24, 2019, granted, now 11,094,394, issued on Aug. 17, 2021.
Prior Publication US 2023/0253064 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/50 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 29/50004 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3427 (2013.01); G11C 29/50016 (2013.01); G11C 2029/5004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
writing a first set of logic states to a subset of memory cells of a memory array;
reading, using a reference voltage, the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;
determining a quantity of differences between the second set of logic states and the first set of logic states based at least in part on reading at the reference voltage; and
performing a recovery operation on the memory array based at least in part on comparing the quantity of differences to an expected quantity of differences that corresponds to the reference voltage.