US 12,230,348 B2
Control method, semiconductor memory, and electronic device
Yoonjoo Eom, Hefei (CN); Lin Wang, Hefei (CN); Zhiqiang Zhang, Hefei (CN); and Yuanyuan Gong, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 17, 2023, as Appl. No. 18/155,124.
Application 18/155,124 is a continuation of application No. PCT/CN2022/093942, filed on May 19, 2022.
Claims priority of application No. 202210307454.8 (CN), filed on Mar. 25, 2022; and application No. 202210498332.1 (CN), filed on May 9, 2022.
Prior Publication US 2023/0307081 A1, Sep. 28, 2023
Int. Cl. G11C 29/14 (2006.01); G11C 29/36 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/14 (2013.01); G11C 29/36 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A control method, applied to a semiconductor memory, the semiconductor memory comprising a Data Mask Pin (DM), the DM being configured to receive an input mask signal of write data, and the method comprising:
when the semiconductor memory is in a preset test mode,
controlling an impedance of the DM to be a first impedance parameter through a first Mode Register (MR), in response to the DM being selected as a test object; or,
controlling the impedance of the DM to be a second impedance parameter through a second MR, in response to the DM not being selected as the test object;
wherein the semiconductor memory further comprises at least one Data Pin (DQ), the DQ is configured to receive or output data, the first MR is configured to indicate that an impedance of the at least one DQ in an output driver state is the first impedance parameter, and the second MR is configured to indicate that the impedance of the at least one DQ in a termination state is the second impedance parameter.