US 12,230,347 B2
System and memory with configurable metadata portion
Jungwon Suh, San Diego, CA (US); Dexter Tamio Chun, San Diego, CA (US); Anand Srinivasan, San Diego, CA (US); Olivier Alavoine, San Diego, CA (US); and Laurent Rene Moll, San Jose, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 24, 2023, as Appl. No. 18/322,997.
Application 18/322,997 is a division of application No. 17/245,981, filed on Apr. 30, 2021, granted, now 11,728,003.
Claims priority of provisional application 63/023,640, filed on May 12, 2020.
Prior Publication US 2023/0298682 A1, Sep. 21, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/1045 (2013.01); G11C 29/18 (2013.01); G11C 29/44 (2013.01); G11C 2029/1202 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory configured to communicate with a host,
the memory comprising a memory array, the memory array comprising a first portion, a second portion, and a third portion;
the memory further configured to:
receive data from the host; and
output the data to the host;
the memory further configured to, in a first mode:
store and output the data in the first portion and the second portion of the memory array, the first portion being addressable by a first address, the second portion being addressable by a second address;
generate first array error-correction code (ECC) based on the data in the first portion; and
store the first array ECC in the third portion; and
the memory further configured to, in a second mode:
store and output the data in the first portion, based on the first address;
receive metadata of the data from the host; and
store and output the metadata in the second portion, based on the first address.