US 12,230,346 B2
Cross-point memory read technique to mitigate drift errors
Hemant P. Rao, Albuquerque, NM (US); Raymond W. Zeng, Sunnyvale, CA (US); Prashant S. Damle, Portland, OR (US); Zion S. Kwok, Burnaby (CA); Kiran Pangal, Fremont, CA (US); and Mase J. Taub, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,421.
Prior Publication US 2022/0415425 A1, Dec. 29, 2022
Int. Cl. G11C 29/00 (2006.01); G11C 7/06 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/06 (2013.01); G11C 29/12005 (2013.01); G11C 29/4401 (2013.01); G11C 29/50004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of cross-point memory cells, each of the cross-point memory cells including a memory element and a switch element; and
circuitry to:
apply a first voltage across the cross-point memory cell, wherein the first voltage has a first magnitude;
after application of the first voltage across the cross-point memory cell, apply a second voltage across the cross-point memory cell, wherein the second voltage has a second magnitude that is lower than the first magnitude; and
determine a state of the cross-point memory cell based on a response of the cross-point memory cell to at least the second voltage, wherein:
the state of the cross-point memory cell is one of at least three states, including a first state, a second state with a first threshold voltage distribution higher than the first state, and a third state with a second threshold voltage distribution higher than the second state, and
the first magnitude is between expected threshold voltages for the second state and the third state.