US 12,230,345 B2
Built-in self-test circuits for memory systems having multiple channels
Jaewon Park, Suwon-si (KR); and Shinhaeng Kang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 29, 2022, as Appl. No. 18/059,462.
Claims priority of application No. 10-2021-0175214 (KR), filed on Dec. 8, 2021; and application No. 10-2022-0065291 (KR), filed on May 27, 2022.
Prior Publication US 2023/0178166 A1, Jun. 8, 2023
Int. Cl. G11C 29/12 (2006.01); G06F 11/00 (2006.01); G11C 29/28 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/28 (2013.01); G11C 29/36 (2013.01); G11C 2029/3602 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a plurality of memory devices having respective arrays of memory cells therein;
a bus electrically coupled to and shared by the plurality of memory devices; and
a memory controller electrically coupled by the bus to the plurality of memory devices, said memory controller comprising a built-in self-test (BIST) circuit, which is configured to transfer a respective command set including a respective at least one test pattern to each of the plurality of memory devices via the bus, and transfer a command trigger signal for driving the respective at least one test pattern to each of the plurality of memory devices via the bus; and
wherein each of the plurality of memory devices comprises a respective command generation circuit, which is configured to store the respective command set received from said BIST circuit and test a corresponding memory cell array based on the respective at least one test pattern, in response to the command trigger signal.