CPC G11C 29/12005 (2013.01) [G11C 2029/1202 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a three-dimensional memory structure comprising layers of data word lines and NAND strings of non-volatile memory cells that extend through the layers of the data word lines, wherein each data word line is connected to a group of the non-volatile memory cells on different NAND strings; and
one or more control circuits in communication with the three-dimensional memory structure, wherein the one or more control circuits are configured to:
concurrently apply a set of test voltages to a corresponding set of the data word lines in the three-dimensional memory structure, wherein the test voltage applied to a particular data word line has a magnitude that depends on which layer the particular data word line resides; and
test the three-dimensional memory structure in response to the set of test voltages concurrently applied to the corresponding set of the data word lines.
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