| CPC G11C 29/04 (2013.01) [G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] | 15 Claims |
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1. A method of operating a memory device, wherein the memory device comprises:
a memory cell array comprising a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; and
a control logic,
wherein the method comprises: detecting a not-open string (N/O string) from the plurality of strings in response to a write command and converting target data to be programmed on a target memory cell in the N/O string so that the target data have a value that limits a number of times a program voltage is applied to the target memory cell,
the memory device further comprising a page buffer circuit configured to latch the target data,
wherein the converting the target data to have the value comprises: converting the target data latched in the page buffer circuit to have the value, and programming the converted target data on the target memory cell through the page buffer circuit,
wherein the target data is latched by 1 bit in each of a plurality of page buffers in the page buffer circuit, and
wherein the method further comprises converting at least one of pieces of data latched in the plurality of page buffers so that the target data has the value, and converting the pieces of data latched in the plurality of page buffers to be the same
wherein a type of target memory cell is a multi-level cell type or more.
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