US 12,230,339 B2
Electronic device and driving method thereof
Sungsoo Chi, Hefei (CN)
Assigned to ChangXin Memory Technologies, Inc., Hefei (CN)
Appl. No. 18/036,036
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed Jul. 12, 2022, PCT No. PCT/CN2022/105237
§ 371(c)(1), (2) Date May 9, 2023,
PCT Pub. No. WO2023/173636, PCT Pub. Date Sep. 21, 2023.
Claims priority of application No. 202210266447.8 (CN), filed on Mar. 17, 2022.
Prior Publication US 2024/0339164 A1, Oct. 10, 2024
Int. Cl. G11C 17/16 (2006.01); G11C 7/08 (2006.01); G11C 17/18 (2006.01)
CPC G11C 17/165 (2013.01) [G11C 7/08 (2013.01); G11C 17/18 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a sensitivity amplifier, wherein the sensitivity amplifier comprises:
a first P-type transistor, wherein a first terminal of the first P-type transistor is connected to a first node, a second terminal is connected to a readout bit line, and a gate of the first P-type transistor is connected to a third node;
a second P-type transistor, wherein a first terminal of the second P-type transistor is connected to the first node, a second terminal of the second P-type transistor is connected to a complementary readout bit line, and a gate of the second P-type transistor is connected to a fourth node;
a first N-type transistor, wherein a first terminal of the first N-type transistor is connected to a second node, a second terminal of the first N-type transistor is connected to the readout bit line, and a gate is connected to a bit line;
a second N-type transistor, wherein a first terminal of the second N-type transistor is connected to the second node, a second terminal is connected to the complementary readout bit line, and a gate is connected to a complementary bit line;
a control circuit, wherein the control circuit is connected to the third node, a fourth node, a preset voltage terminal, and a first control signal terminal, for responding to a signal of the first control signal terminal to connect the preset voltage terminal to the third node and a fourth node; and
a voltage adjustment circuit, wherein the voltage adjustment circuit is connected to the preset voltage terminal and an adjustment signal terminal, and wherein the voltage adjustment circuit inputs a preset voltage signal to the preset voltage terminal according to an adjustment signal from the adjustment signal terminal.