| CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/25 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
a plurality of memory cells, each of the plurality of memory cells is operatively coupled to a word line, a gate control line, a bit line, and a control line;
wherein each of the plurality of memory cells comprises a first transistor, a second transistor, a third transistor, a diode-connected transistor, and a capacitor coupled to one another in series; and
wherein the capacitor is coupled between the bit line and a common node between the second transistor and the third transistor.
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