CPC G11C 17/16 (2013.01) [G11C 7/24 (2013.01); G11C 17/18 (2013.01)] | 20 Claims |
1. A memory device comprising:
an eFuse cell array in which unit cells of different types are alternately disposed,
wherein each of the unit cells of different types comprises a PN diode, a first NMOS transistor, and a fuse,
wherein a first type unit cell and a second type unit cell are connected to each other through a common node, and
wherein the first type unit cell and the second type unit cell are disposed side by side in a horizontal direction relative to the common node to form a bilaterally symmetrical structure.
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