US 12,230,336 B2
Semiconductor memory device, and method operating based on status checker
Byoung Sung You, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 4, 2022, as Appl. No. 17/881,012.
Claims priority of application No. 10-2022-0032965 (KR), filed on Mar. 16, 2022.
Prior Publication US 2023/0317183 A1, Oct. 5, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/1039 (2013.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of memory blocks each including a plurality of physical pages;
a peripheral circuit configured to perform a program operation, an erase operation, or a read operation on a selected memory block among the plurality of memory blocks;
control logic capable of controlling the program operation, the erase operation, or the read operation of the peripheral circuit; and
a status checker configured to check a ratio of programmed pages among the physical pages included in the plurality of memory blocks,
wherein the peripheral circuit includes a plurality of page buffers connected to the plurality of memory blocks through bit lines,
each of the plurality of page buffers includes a respective one of a plurality of latches, and
the status checker is configured to check the ratio of the programmed pages based on data stored in the plurality of latches.