US 12,230,335 B2
Data latch programming algorithm for multi-bit-per-cell memory devices
Toru Miwa, Yokohama (JP); and Fumiaki Toyama, Cupertino, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 13, 2022, as Appl. No. 17/838,717.
Prior Publication US 2023/0402113 A1, Dec. 14, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/1039 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method of multi-stage programming of a multi-bit-per-cell memory array, the method comprising:
receiving first program data corresponding to a first page level into a first data latch;
performing an initial program stage of the multi-stage programming to generate a plurality of threshold voltage distributions from an initial threshold distribution based on the first program data corresponding to the first page level, wherein the initial threshold voltage distribution represents an initial erase state; and
performing one or more additional program stages corresponding to one or more additional page levels, wherein performing each additional program stage comprises receiving additional programming data corresponding to a current additional page level into the first data latch and performing a program loop for each threshold voltage distribution generated during a prior program stage, the performing the program loop comprising splitting the threshold voltage distribution generated during the prior program stage into two new threshold voltage distributions based on data stored in a second data latch and the additional programming data.