US 12,230,334 B2
Dynamic program caching
Aliasgar S. Madraswala, Folsom, CA (US); Ali Khakifirooz, Brookline, MA (US); Bhaskar Venkataramaiah, Folsom, CA (US); Sagar Upadhyay, Folsom, CA (US); and Yogesh B. Wakchaure, Folsom, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Mar. 31, 2022, as Appl. No. 17/710,978.
Prior Publication US 2023/0317182 A1, Oct. 5, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a dynamic program cache mode that is any one of active and inactive;
a controller to reduce a latency of a program operation responsive to a determination that the dynamic program cache mode is active, the program operation to program one or more pages of at least three pages in a multi-level cell (MLC) memory at multiple threshold voltage levels, including to, for each threshold voltage level of the multiple threshold voltage levels:
determine a presence of page data in a first page to program in the MLC memory,
determine an absence of page data in a next page to program in the MLC memory, issue a data I/O (input/output) operation to load the first page determined as having data to program at a threshold voltage level of the multiple threshold voltage levels, and
issue one or more portions of the program operation to execute, at least in part, concurrently with one or more data I/O operations issued to load one or more next pages determined as having no data to program at the threshold voltage level.