US 12,230,333 B2
Bit line modulation to compensate for cell source variation
Anirudh Amarnath, San Jose, CA (US); Aravind Suresh, San Jose, CA (US); and Abhijith Prakash, Milpitas, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Sep. 28, 2022, as Appl. No. 17/954,489.
Prior Publication US 2024/0105269 A1, Mar. 28, 2024
Int. Cl. G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/102 (2013.01); G11C 16/24 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method, for reading data from non-volatile storage, comprising:
determining a first bit line level based on a first programmed data state that is being sensed, the first programmed data state being associated with a first threshold voltage range;
applying the first bit line level to a plurality of selected bit lines during sensing of the first programmed data state;
determining a second bit line level based on a second programmed data state that is being sensed, the second programmed data state being associated with a second threshold voltage range that is greater than the first threshold voltage range, and the second bit line level being greater than the first bit line level; and
applying the second bit line level to the plurality of selected bit lines during sensing of the second programmed data state.