US 12,230,332 B2
Suspending memory erase operations to perform higher priority memory commands
Shakeel Isamohiuddin Bukhari, San Jose, CA (US); and Mark Ish, Manassas, VA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 14, 2022, as Appl. No. 17/931,935.
Claims priority of provisional application 63/374,095, filed on Aug. 31, 2022.
Prior Publication US 2024/0071520 A1, Feb. 29, 2024
Int. Cl. G11C 16/26 (2006.01); G11C 16/16 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/16 (2013.01); G11C 16/32 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
detect a pending host read command during an erase operation that is being performed by the memory device,
wherein the erase operation includes an erase pulse stage and an erase verify stage;
and
selectively suspend the erase operation based on detecting the pending host read command and based on:
a first condition if the erase pulse stage is being performed, and
a second condition if the erase verify stage is being performed.