US 12,230,331 B2
Memory device
Hiroshi Maejima, Setagaya Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2022, as Appl. No. 17/901,459.
Claims priority of application No. 2022-029798 (JP), filed on Feb. 28, 2022.
Prior Publication US 2023/0298673 A1, Sep. 21, 2023
Int. Cl. G11C 16/26 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 16/26 (2013.01) [H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A three-dimensional NAND flash nonvolatile memory device comprising:
a first memory pillar extending in a first direction;
a first word line extending in a second direction, the second direction intersecting with the first direction;
a first memory cell provided at an intersecting point of the first memory pillar and the first word line;
a second memory pillar extending in the first direction and parallel to the first memory pillar;
a second word line extending in the second direction and parallel to the first word line;
a second memory cell provided at an intersecting point of the second memory pillar and the second word line, each of the first memory cell and the second memory cell corresponding to a first column address;
a first sense amplifier unit;
a first bit line connected between the first memory cell and the first sense amplifier unit; and
a second bit line connected between the second memory cell and the first sense amplifier unit, wherein the first bit line and the second bit line are located between the first and second word lines and the first sense amplifier in the first direction.