| CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/28 (2013.01); G11C 16/3404 (2013.01)] | 19 Claims |
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1. A flash memory device comprising:
a memory cell array connected with a plurality of word lines including a selected word line, a previous word line on which programming is performed before the selected word line, and a next word line on which programming is performed after the selected word line; and
control logic configured to:
perform threshold voltage compensation on the plurality of word lines through a data recover read operation,
determine that the next word line is a dummy word line,
in response to determining that the next word line is a dummy word line, set the previous word line as an aggressor word line,
perform a data recover read operation on the aggressor word line, and
perform the threshold voltage compensation on the selected word line based on a result of the data recover read operation of the aggressor word line.
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