| CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |

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1. A semiconductor device comprising:
a cell area including
a plurality of word lines stacked on a substrate,
at least one ground select line between the plurality of word lines and the substrate, and
a plurality of channel structures extending in a first direction, perpendicular to the substrate, and passing through the plurality of word lines and the at least one ground select line; and
a peripheral circuit area including peripheral circuits configured to
control the cell area, and
input a program voltage to at least a portion of the plurality of word lines in an order of approaching the substrate along the first direction,
input a first ground select bias voltage to the at least one ground select line during a first program time for inputting a first program voltage to a program word line among the plurality of word lines, and
input a second ground select bias voltage having a magnitude different from a magnitude of the first ground select bias voltage to the at least one ground select line during a second program time for inputting a second program voltage having a magnitude different from a magnitude of the first program voltage to the program word line.
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