US 12,230,327 B2
Semiconductor memory device
Hiroshi Maejima, Setagaya Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 30, 2023, as Appl. No. 18/524,458.
Application 18/524,458 is a continuation of application No. 18/080,524, filed on Dec. 13, 2022, granted, now 11,875,851.
Application 18/080,524 is a continuation of application No. 17/502,573, filed on Oct. 15, 2021, granted, now 11,568,936, issued on Jan. 31, 2023.
Application 17/502,573 is a continuation of application No. 16/883,591, filed on May 26, 2020, granted, now 11,176,998, issued on Nov. 16, 2021.
Application 16/883,591 is a continuation of application No. 16/540,529, filed on Aug. 14, 2019, granted, now 10,706,931, issued on Jul. 7, 2020.
Application 16/540,529 is a continuation of application No. 15/977,543, filed on May 11, 2018, granted, now 10,418,104, issued on Sep. 17, 2019.
Application 15/977,543 is a continuation of application No. 15/498,029, filed on Apr. 26, 2017, granted, now 10,008,269, issued on Jun. 26, 2018.
Application 15/498,029 is a continuation of application No. 15/231,715, filed on Aug. 8, 2016, granted, now 9,666,296, issued on May 30, 2017.
Claims priority of application No. 2016-040290 (JP), filed on Mar. 2, 2016.
Prior Publication US 2024/0096419 A1, Mar. 21, 2024
Int. Cl. G11C 16/28 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01); G11C 16/3427 (2013.01); G11C 16/32 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first wiring;
a second wiring;
a first memory string including:
a first select transistor having one end coupled to the first wiring;
a first memory cell transistor having one end coupled to the other end of the first select transistor;
a second memory cell transistor having one end coupled to the other end of the first memory cell transistor;
a second select transistor having one end coupled to the other end of the second memory cell transistor; and
a third select transistor having one end coupled to the other end of the second select transistor and the other end coupled to the second wiring;
a second memory string including:
a fourth select transistor having one end coupled to the first wiring;
a third memory cell transistor having one end coupled to the other end of the fourth select transistor;
a fourth memory cell transistor having one end coupled to the other end of the third memory cell transistor;
a fifth select transistor having one end coupled to the other end of the fourth memory cell transistor; and
a sixth select transistor having one end coupled to the other end of the fifth select transistor and the other end coupled to the second wiring;
a first select gate line coupled to a gate of the first select transistor;
a second select gate line coupled to a gate of the second select transistor;
a third select gate line coupled to a gate of the fourth select transistor;
a fourth select gate line coupled to a gate of the fifth select transistor;
a fifth select gate line coupled to a gate of the third select transistor and a gate of the sixth select transistor;
a first word line coupled to a gate of the first memory cell transistor and a gate of the third memory cell transistor;
a second word line coupled to a gate of the second memory cell transistor and a gate of the fourth memory cell transistor; and
a voltage generation circuit, wherein
during a first period of the read operation to read data from the first memory cell transistor, the voltage generation circuit:
applies a first voltage greater than the ground voltage to the first selection gate line,
applies a second voltage less than the first voltage but greater than the ground voltage to the third selection gate line,
applies a third voltage to the first word line,
applies an fourth voltage greater than the third voltage to the second word line,
applies an fifth voltage that is a voltage to turn off the fifth select transistor to the fourth select gate line, and
applies an sixth voltage greater than the ground voltage to the fifth select gate line.