US 12,230,326 B2
Semiconductor memory device with conductive layers separated between memory blocks
Keisuke Suda, Yokkaichi Mie (JP); Ryota Suzuki, Yokkaichi Mie (JP); and Kenta Yamada, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 13, 2022, as Appl. No. 17/943,487.
Claims priority of application No. 2022-048390 (JP), filed on Mar. 24, 2022.
Prior Publication US 2023/0307050 A1, Sep. 28, 2023
Int. Cl. G11C 16/06 (2006.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 5/025 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of memory blocks arranged in a first direction; and
a plurality of bit lines that extend in the first direction, are arranged in a second direction intersecting with the first direction, and are arranged with the plurality of memory blocks in a third direction intersecting with the first direction and the second direction, wherein
each of the plurality of memory blocks includes:
a plurality of first conductive layers arranged in the third direction;
a second conductive layer disposed on a side opposite to the plurality of bit lines in the third direction with respect to the plurality of first conductive layers;
a plurality of semiconductor layers that extend in the third direction, are opposed to the plurality of first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the plurality of bit lines; and
a plurality of electric charge accumulating films disposed between the plurality of first conductive layers and the plurality of semiconductor layers,
the plurality of first conductive layers are separated between the plurality of memory blocks, and
the second conductive layer is separated between the plurality of memory blocks.