US 12,230,325 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
Alyssa N. Scarbrough, Boise, ID (US); John D. Hopkins, Meridian, ID (US); Collin Howder, Boise, ID (US); and Jordan D. Greenlee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 23, 2021, as Appl. No. 17/409,300.
Prior Publication US 2023/0055319 A1, Feb. 23, 2023
Int. Cl. H01L 21/768 (2006.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion having an uppermost source tier, the lower portion comprising an upper second tier above the uppermost source tier and comprising insulative material;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion, and forming channel-material strings that extend through the upper portion and through the upper second tier to the uppermost source tier of the lower portion;
forming horizontally-elongated lines in the upper second tier above the uppermost source tier and longitudinally-along opposing lateral edges of the memory-block regions, material of the lines being of different composition from that of the insulative material in the upper second tier that is laterally-between the lines;
forming horizontally-elongated trenches into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion; and
directly electrically coupling channel material of the channel-material strings with conductive material that is in the uppermost source tier and with the conductor material that is in the conductor tier.