US 12,230,324 B2
Masking circuit and pre-charge circuit applicable to content addressable memory
I-Hao Chiang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Dec. 29, 2021, as Appl. No. 17/564,251.
Claims priority of application No. 110109138 (TW), filed on Mar. 15, 2021.
Prior Publication US 2022/0293179 A1, Sep. 15, 2022
Int. Cl. G11C 15/00 (2006.01); G11C 11/408 (2006.01); G11C 11/417 (2006.01); G11C 11/419 (2006.01); G11C 15/04 (2006.01); H03K 19/20 (2006.01)
CPC G11C 15/04 (2013.01) [G11C 11/4085 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01); H03K 19/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A masking circuit of a content addressable memory (CAM), the masking circuit comprising:
a masking control circuit configured to generate a masking signal according to a first signal and a second signal, wherein when both the first signal and the second signal are at a first level, the masking signal is a first masking signal, and when the first signal and the second signal are at different levels respectively, the masking signal is a second masking signal different from the first masking signal; and
a level control circuit configured to generate a level control signal according to the masking signal and thereby determine whether to pull a voltage level of an output terminal to a predetermined level,
wherein the output terminal is coupled to a match line of the CAM; when the masking signal is the first masking signal, the level control circuit pulls the voltage level of the output terminal to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level of the output terminal,
wherein the first signal is a word line signal for the CAM, and the second signal is a write enablement signal for the CAM.