US 12,230,322 B2
Memory device including memory cell including variable resistance element and switching element
Ryousuke Takizawa, Naka Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 13, 2022, as Appl. No. 17/943,432.
Claims priority of application No. 2022-044263 (JP), filed on Mar. 18, 2022.
Prior Publication US 2023/0317155 A1, Oct. 5, 2023
Int. Cl. G11C 11/24 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0038 (2013.01); G11C 13/0069 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first interconnect;
a second interconnect;
a first memory cell between the first interconnect and the second interconnect, the first memory cell comprising a first variable resistance element and a first switching element, and the first switching element being configured to transition from an ON state to an OFF state in response to a voltage applied between two terminals of the first switching element being decreased; and
a read circuit configured to:
place the second interconnect in a floating state, and
after placing the second interconnect in the floating state, and based on a comparison between a first voltage of the second interconnect at a time point of the first switching element becoming the OFF state and a second voltage, either:
apply a third voltage to the second interconnect and then place the second interconnect in the floating state, or
apply a fourth voltage lower than the third voltage to the second interconnect without applying the third voltage to the second interconnect.