US 12,230,321 B2
Device with neural network
Jung-Hoon Chun, Suwon-si (KR); Jiho Song, Suwon-si (KR); Yoonmyung Lee, Suwon-si (KR); and Jua Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 1, 2022, as Appl. No. 17/830,004.
Claims priority of application No. 10-2021-0179808 (KR), filed on Dec. 15, 2021.
Prior Publication US 2023/0186986 A1, Jun. 15, 2023
Int. Cl. G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 11/54 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 11/1673 (2013.01); G11C 11/54 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01); G11C 2211/5634 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device with a neural network, comprising:
a plurality of synaptic memory cells, disposed along a first output line, configured to generate a column signal based on resistive memory elements and input signals being received through a plurality of input lines, each of the plurality of synaptic memory cells comprising a resistive memory element having either one of a first resistance value or a second resistance value;
a plurality of reference memory cells, disposed along a reference line with sharing the plurality of input lines with the plurality of synaptic memory cells respectively, configured to generate a reference signal based on reference memory elements and the input signals, each of the plurality of reference memory cells comprising a reference memory element having the second resistance value different from the first resistance value; and
an output circuit configured to generate an output signal, for the first output line, indicating a difference between the column signal and the reference signal,
wherein the output circuit is configured to generate, as the output signal, a current corresponding to an integer multiple of a net current that is a difference between a first current based on a resistive memory element with the first resistance value and a second current based on a resistive memory element with the second resistance value.