	US 12,230,317 B2
	Column multiplexer circuitry
Lalit Gupta, Cupertino, CA (US); Fakhruddin Ali Bohra, San Jose, CA (US); Shri Sagar Dwivedi, San Jose, CA (US); and Vidit Babbar, Bangalore (IN)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Sep. 18, 2023, as Appl. No. 18/369,794.
Application 18/369,794 is a continuation of application No. 16/990,951, filed on Aug. 11, 2020, granted, now 11,763,880.
Claims priority of application No. 202041013913 (IN), filed on Mar. 30, 2020.
Prior Publication US 2024/0005985 A1, Jan. 4, 2024
Int. Cl. G11C 11/418 (2006.01); G11C 11/419 (2006.01)

CPC G11C 11/418 (2013.01) [G11C 11/419 (2013.01)]

19 Claims

1. An integrated circuit, comprising:

first and second multi-bank arrays;

multi-bank control circuitry comprising control logic circuitry including latch circuitry and an output buffer, wherein:

the latch circuitry is configured to: receive a clock signal, a bank address, a mixed sense amplifier enable signal, and transmit an output signal to the output buffer, and

the output buffer is configured to output a bank multiplexer selection signal; and

multi-bank multiplexer circuitry configured to select output data from one of the first or the second multi-bank arrays based on the bank multiplexer selection signal received from the multi-back control circuitry.