US 12,230,316 B2
Memory device including memory cells and edge cells
Atuk Katoch, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jan. 12, 2024, as Appl. No. 18/412,380.
Application 18/412,380 is a continuation of application No. 17/883,998, filed on Aug. 9, 2022, granted, now 11,900,994.
Application 17/883,998 is a continuation of application No. 17/220,701, filed on Apr. 1, 2021, granted, now 11,488,661.
Prior Publication US 2024/0153550 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/14 (2006.01); G11C 11/417 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/417 (2013.01) [G11C 5/148 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of memory cells;
at least one first edge cell; and
at least one second edge cell, wherein
the at least one first edge cell and the at least one second edge cell are arranged respectively at two opposite sides of the array of memory cells, and
at least one edge cell, among the at least one first edge cell and the at least one second edge cell, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.