US 12,230,315 B2
Model for predicting memory system performance
Vamsi Pavan Rayaprolu, Santa Clara, CA (US); and Aswin Thiruvengadam, El Dorado Hills, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 12, 2022, as Appl. No. 17/819,567.
Prior Publication US 2024/0055046 A1, Feb. 15, 2024
Int. Cl. G11C 11/4076 (2006.01); G11C 7/24 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 7/24 (2013.01); G11C 11/4076 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method, comprising:
performing a first set of read operations at a memory device of a memory system;
generating information indicating a performance of the memory device associated with performing the first set of read operations;
updating one or more coefficients of a model that correlates the information indicating the performance of the memory device with a read window associated with read operations of the memory device, wherein the model comprises a linear regression model, a logarithmic regression model, or a combination thereof; and
performing a second set of read operations at the memory device using one or more updated parameters based on the one or more updated coefficients.