US 12,230,314 B2
Semiconductor device, memory device, and electronic device
Tatsuya Onuki, Kanagawa (JP); Takanori Matsuzaki, Kanagawa (JP); Kiyoshi Kato, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 18, 2023, as Appl. No. 18/135,779.
Application 18/135,779 is a continuation of application No. 17/377,757, filed on Jul. 16, 2021, granted, now 11,657,867.
Application 17/377,757 is a continuation of application No. 16/640,206, granted, now 11,074,962, issued on Jul. 27, 2021, previously published as PCT/IB2018/056412, filed on Aug. 24, 2018.
Claims priority of application No. 2017-170814 (JP), filed on Sep. 6, 2017; and application No. 2018-034610 (JP), filed on Feb. 28, 2018.
Prior Publication US 2023/0253031 A1, Aug. 10, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 11/4091 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4091 (2013.01) [G11C 5/02 (2013.01); G11C 5/063 (2013.01); H10B 12/30 (2023.02)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a sense amplifier comprising a first transistor;
a bit line over the sense amplifier; and
a memory cell array over the bit line,
wherein the memory cell array comprises a second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor through the bit line,
wherein a top surface of the bit line is connected to a bottom surface of a semiconductor layer of the second transistor through a conductor, and
wherein the semiconductor layer includes a metal oxide.