US 12,230,313 B2
Vertical memory device
Seung-Hwan Kim, Seoul (KR); Su-Ock Chung, Seoul (KR); and Seon-Yong Cha, Chungcheongbuk-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 18, 2023, as Appl. No. 18/542,769.
Application 18/542,769 is a continuation of application No. 17/739,944, filed on May 9, 2022, granted, now 11,887,654.
Application 17/739,944 is a continuation of application No. 16/854,382, filed on Apr. 21, 2020, granted, now 11,355,177, issued on Jun. 7, 2022.
Claims priority of application No. 10-2019-0084689 (KR), filed on Jul. 12, 2019.
Prior Publication US 2024/0119994 A1, Apr. 11, 2024
Int. Cl. G11C 11/24 (2006.01); G11C 11/408 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4085 (2013.01) [H01L 23/528 (2013.01); H01L 28/86 (2013.01); H10B 12/30 (2023.02); H10B 12/50 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a peripheral circuit portion including a sub word line driver circuit and a sense amplifier;
a memory cell mat including a sub word line stack with multi-step end structure; and
an interconnection that electrically connects the multi-step end structure of the sub word line stack and the sub word line driver circuit to each other,
wherein the sub word line driver circuit is vertically overlapped with the multi-step end structure of the sub word line stack, and
wherein the peripheral circuit portion is positioned over the memory cell mat.