US 12,230,310 B2
Memory and operation method thereof
Woongrae Kim, Gyeonggi-do (KR); and Chul Moon Jung, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 4, 2022, as Appl. No. 17/980,943.
Claims priority of application No. 10-2022-0033481 (KR), filed on Mar. 17, 2022.
Prior Publication US 2023/0298653 A1, Sep. 21, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/401 (2006.01); G11C 11/4074 (2006.01); G06F 3/06 (2006.01); G11C 11/4078 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/401 (2013.01); G11C 11/406 (2013.01); G11C 11/40618 (2013.01); G11C 11/4074 (2013.01); G06F 3/0625 (2013.01); G11C 11/4078 (2013.01); G11C 2211/4067 (2013.01); G11C 2211/4068 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An operation method of a memory, the operation method comprising:
entering a self-refresh mode;
increasing a level of a back-bias voltage in response to entering the self-refresh mode;
performing self-refresh operations in a first cycle;
confirming that the level of the back-bias voltage reaches a level of a first threshold voltage; and
performing the self-refresh operations in a second cycle longer than the first cycle in response to confirming that the level of the back-bias voltage reaches the level of the first threshold voltage.