US 12,230,309 B2
Dual-precision analog memory cell and array
Zhichao Lu, San Jose, CA (US); and Liang Zhao, Sunnyvale, CA (US)
Assigned to Hefei Reliance Memory Limited, Hefei (CN)
Filed by HEFEI RELIANCE MEMORY LIMITED, Hefei (CN)
Filed on Dec. 4, 2023, as Appl. No. 18/528,311.
Application 18/528,311 is a division of application No. 18/082,005, filed on Dec. 15, 2022, granted, now 11,887,645.
Application 18/082,005 is a continuation of application No. 17/308,675, filed on May 5, 2021, granted, now 11,551,739, issued on Jan. 10, 2023.
Application 17/308,675 is a continuation of application No. 16/693,332, filed on Nov. 24, 2019, granted, now 11,069,391, issued on Jul. 20, 2021.
Claims priority of provisional application 62/773,991, filed on Nov. 30, 2018.
Prior Publication US 2024/0105247 A1, Mar. 28, 2024
Int. Cl. G11C 14/00 (2006.01); G06N 3/06 (2006.01); G06N 5/04 (2023.01); G11C 11/22 (2006.01); G11C 11/4074 (2006.01); G11C 11/56 (2006.01)
CPC G11C 11/2273 (2013.01) [G06N 3/06 (2013.01); G06N 5/04 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/4074 (2013.01); G11C 11/5642 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a dual-precision analog memory cell comprising:
a non-volatile memory element having an input terminal, a first output terminal, and a second output terminal,
a volatile memory element comprising:
a first transistor having a drain electrically coupled to the input terminal of the non-volatile memory element, and
a second transistor having a source electrically coupled to the input terminal of the non-volatile memory element; and
a controller configured to increase a weight stored in the dual-precision analog memory cell by:
biasing a source of the first transistor to a high supply voltage,
biasing a drain of the second transistor to a low supply voltage,
biasing a gate of the second transistor at a low voltage,
biasing the first and second output terminals of the non-volatile memory element at the low voltage, and
applying a high voltage followed by a low voltage pulse to a gate of the first transistor, wherein the high voltage is higher than the low voltage.