US 12,230,232 B2
Configurable types of write operations
Giuseppe Cariello, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 9, 2022, as Appl. No. 17/818,613.
Prior Publication US 2024/0054971 A1, Feb. 15, 2024
Int. Cl. G09G 5/08 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01)
CPC G09G 5/08 (2013.01) [G06F 13/1673 (2013.01); G11C 7/10 (2013.01); G11C 16/102 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory system, comprising:
processing circuitry configured to couple with one or more memory devices, wherein the processing circuitry is configured to cause the memory system to:
receive a write command to write data in a zone of the memory system associated with a zoned namespace architecture for the memory system;
identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command, the cursor being associated with a type of a write operation, the type of the write operation being based at least in part on a quantity of data associated with the cursor;
write, to a sub-zone of the zone, using the type of the write operation in accordance with the quantity of data and based at least in part on identifying the physical address, the type of the write operation being one of a first type of the write operation associated with writing information in multiple planes of the memory system or a second type of the write operation associated with writing information in one plane of the memory system; and
write, to a logical-to-physical mapping, an indication of the type of the write operation used to write the data into the sub-zone based at least in part on writing the data to the sub-zone.