| CPC G09G 3/3266 (2013.01) [G09G 2310/08 (2013.01)] | 18 Claims |
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1. A scan circuit, comprising a plurality of stages, wherein a respective stage of the scan circuit comprises a respective scan unit configured to provide a control signal to at least a row of subpixels;
wherein the respective scan unit comprises an input subcircuit configured to receive from an input terminal a start signal or an output signal from a previous scan unit of a previous stage, a first processing subcircuit, a second processing subcircuit, and an output subcircuit configured to output an output signal from an output terminal;
wherein the output subcircuit comprises a first output transistor;
wherein the input subcircuit comprises a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node; and
the first node is coupled to a gate electrode of the first output transistor;
wherein the first processing subcircuit comprises a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal; and
the first reference terminal is configured to receive a first reference signal;
wherein the first processing subcircuit further comprises a first control transistor coupled between a second node and the first reference terminal;
a gate electrode of the first control transistor is coupled to the input terminal, and is configured to receive the start signal or the output signal from the previous scan unit of the previous stage;
a source electrode of the first control transistor is coupled to the first reference terminal, and is configured to receive the first reference signal; and
a drain electrode of the first control transistor is coupled to the second node, which is coupled to gate electrodes of the first switch transistor and the second switch transistor.
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