CPC G09G 3/3266 (2013.01) [H10K 59/1201 (2023.02); H10K 59/131 (2023.02); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |
1. A display substrate, comprising a display area and a bezel area located on at least one side of the display area, wherein:
the bezel area comprises a circuit area and a partition area which are sequentially arranged in a direction away from the display area, the circuit area comprises a third gate driving circuit, a second gate driving circuit and a first gate driving circuit which are sequentially arranged in the direction away from the display area, the partition area comprises a power supply line, the power supply line comprises a first branch and a second branch;
in a direction perpendicular to the display substrate, the display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence on a base substrate, the first semiconductor layer comprises active layers of a plurality of polysilicon transistors, the first conductive layer comprises gate electrodes of the plurality of polysilicon transistors and a first plate of a storage capacitor, the second conductive layer comprises a second plate of the storage capacitor, the second semiconductor layer includes active layers of a plurality of oxide transistors, the third conductive layer comprises gate electrodes of the plurality of oxide transistors, the fourth conductive layer comprises first electrodes and second electrodes of the plurality of polysilicon transistors, first electrodes and second electrodes of the plurality of oxide transistors and the first branch of the power supply line, the fifth conductive layer comprises the second branch of the power supply line; and
there is an overlapping area between an orthographic projection of the second branch of the power supply line on the base substrate and an orthographic projection of the first branch of the power supply line on the base substrate, and there is an overlapping area between the orthographic projection of the second branch of the power supply line on the base substrate and an orthographic projection of the first gate driving circuit on the base substrate; there is no overlapping area between the orthographic projection of the first branch of the power supply line on the base substrate and the orthographic projection of the first gate driving circuit on the base substrate.
|