a plurality of pairs of gate lines, each pair of gate lines comprising a first gate line and a second gate line;

a plurality of data lines; and

a pixel array, comprising a plurality of pixel units arranged into a plurality of rows and a plurality of columns;

wherein each of the plurality of pixel units comprises a scan signal terminal, a data signal terminal and a reset signal terminal, the plurality of rows of pixel units are in one- to-one correspondence with the plurality of pairs of gate lines, and the pixel units of each column corresponds to one data line of the plurality of data lines;

the scan signal terminal of a pixel unit of an nth column in an mth row of pixel units is connected to the first gate line in an mth pair of gate lines to receive a first scan signal; m and n are positive integers;

the scan signal terminal of a pixel unit of an (n+1) th column in the mth row of pixel units is connected to the second gate line in the mth pair of gate lines to receive a second scan signal;

the reset signal terminal of the pixel unit of the (n+1) th column in the mth row of pixel units is connected to the first gate line in the mth pair of gate lines to receive the first scan signal serving as a first reset signal;

data signal terminals of the pixel units of each column are connected to a corresponding data line to receive a data signal;

wherein the reset signal terminal of the pixel unit of the nth column in the mth row of pixel units is connected to the first gate line of an (m-1) th pair of gate lines to receive the first scan signal, and the first scan signal is provided by the first gate line of the (m- 1) th pair of gate lines and used as a second reset signal, m is an integer greater than 1;

a scan signal terminal of a pixel unit of an nth column in an (m-1) th row of pixel units is connected to the first gate line of the (m-1) th pair of gate lines.