a base substrate;

a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of partition control signal lines, a plurality of first initialization signal lines and a plurality of second scanning signal lines disposed on the base substrate; and

a plurality of sub-pixels disposed on the base substrate and located in the display region, wherein the plurality of sub-pixels are arranged in an array in a first direction and a second direction in the display region, the first direction intersects the second direction, and at least one of the plurality of sub-pixels comprises a pixel circuit and a light emitting device,

wherein the pixel circuit comprises a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor;

wherein the switch transistor is electrically connected to at least one of the plurality of first scanning signal lines and at least one of the plurality of data signal lines, the first initialization transistor is electrically connected to at least one of the plurality of first initialization signal lines and at least one of the plurality of second scanning signal lines, the drive transistor is electrically connected to the light emitting device, and the first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one of the plurality of partition control signal lines;

wherein the switch transistor is configured to: transmit a data signal on the data signal line to the first partition control transistor in response to a first scanning signal on the first scanning signal line; the first initialization transistor is configured to: transmit a first initialization signal on the first initialization signal line to the first partition control transistor in response to a second scanning signal on the second scanning signal line; the first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase; and the drive transistor is configured to: provide a drive signal to the light emitting device in response to a voltage difference between the gate electrode of the drive transistor and a first electrode of the drive transistor; and

wherein in one and same pixel circuit, in the second direction, an orthographic projection of the first partition control transistor on the base substrate is located between an orthographic projection of the first initialization transistor on the base substrate and an orthographic projection of the drive transistor on the base substrate.