US 12,230,184 B2
Display module having low difference in pixel luminance and display apparatus
Qiujie Su, Beijing (CN); Yingmeng Miao, Beijing (CN); Dongchuan Chen, Beijing (CN); Yanping Liao, Beijing (CN); Seungmin Lee, Beijing (CN); Xibin Shao, Beijing (CN); and Xiaofeng Yin, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/634,733
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Mar. 29, 2021, PCT No. PCT/CN2021/083618
§ 371(c)(1), (2) Date Feb. 11, 2022,
PCT Pub. No. WO2022/204877, PCT Pub. Date Oct. 6, 2022.
Prior Publication US 2023/0377506 A1, Nov. 23, 2023
Int. Cl. G09G 3/20 (2006.01); G06F 3/041 (2006.01)
CPC G09G 3/2096 (2013.01) [G06F 3/0412 (2013.01); G06F 3/0416 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A display module, comprising: a display panel, wherein the display panel comprises an active area and a non-active area surrounding the active area, the non-active area comprises a first bonding area located at at least one side of two opposite sides of the active area;
the first bonding area at the at least one side is provided with at least one chip group, and a group of first PLG wirings corresponding to each of the chip groups; each of the chip groups comprises at least two groups of chip units, each group of the chip units comprises at least one gate drive chip; each group of the first PLG wirings comprises a first wiring and at least one second wiring, and input ends of the first wiring and each of the second wirings are connected with a same power signal end;
wherein, power pins of any two adjacent instances of the gate drive chips are connected by the first wiring, and each of the second wirings surrounds and passes through each of the gate drive chips; from a direction close to the power signal end to a direction far away from the power signal end, the first wiring connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units.