US 12,229,870 B2
Apparatus and method for acceleration data structure refit
Michael Apodaca, Folsom, CA (US); Carsten Benthin, Voelklingen (DE); Kai Xiao, San Jose, CA (US); Carson Brownlee, Austin, TX (US); Timothy Rowley, Austin, TX (US); Joshua Barczak, Timonium, MD (US); and Travis Schluessler, Berthoud, CO (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Nov. 8, 2022, as Appl. No. 17/982,766.
Application 17/982,766 is a continuation of application No. 17/032,964, filed on Sep. 25, 2020, granted, now 11,501,484.
Application 17/032,964 is a continuation of application No. 16/235,391, filed on Dec. 28, 2018, abandoned.
Prior Publication US 2023/0162428 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/06 (2011.01); G06F 7/14 (2006.01); G06F 9/38 (2018.01); G06F 16/901 (2019.01); G06N 3/02 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 5/70 (2024.01)
CPC G06T 15/06 (2013.01) [G06F 7/14 (2013.01); G06F 9/3877 (2013.01); G06F 16/9027 (2019.01); G06N 3/02 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 5/70 (2024.01); Y02D 10/00 (2018.01)] 16 Claims
OG exemplary drawing
 
1. A processor comprising:
a central processing unit (CPU) comprising a first plurality cores;
a graphics processor comprising a second plurality of cores to execute program code to render images;
a memory controller to couple the first and second plurality of cores to a system memory device, the system memory device to be accessible by both of the first plurality of cores of the CPU and the second plurality of cores of the graphics processor using a same virtual address space; and
execution circuitry associated with at least one core of the second plurality of cores to execute at least a portion of the graphics program code to perform:
constructing an acceleration data structure based on a plurality of primitives located within a three dimensional (3D) space, the acceleration data structure comprising nodes arranged in a hierarchy, each node associated with a bounding volume within the 3D space, the nodes including:
a plurality of leaf nodes at a bottom of the hierarchy, each leaf node bounding one or more of the primitives; and
one or more inner nodes, each inner node bounding one or more leaf nodes,
traversing one or more rays through the acceleration data structure,
identifying intersections between the one or more rays and one or more of the primitives, and
performing a refit operation to adjust nodes of the acceleration data structure in response to detecting movement of one or more of the primitives to new locations in the 3D space, the refit operation performed entirely on the graphics processor, comprising:
adjusting one or more of the leaf nodes based on the new locations of the one or more primitives, wherein the adjusting comprises moving bounding volumes of the leaf nodes to reflect the new locations of the one or more primitives; and
adjusting an inner node if a leaf node bounded by the inner node was adjusted.