US 12,229,673 B2
Sparsity-aware datastore for inference processing in deep neural network architectures
Deepak Mathaikutty, Chandler, AZ (US); Arnab Raha, Santa Clara, CA (US); Raymond Sung, San Francisco, CA (US); Debabrata Mohapatra, Santa Clara, CA (US); and Cormac Brick, San Francisco, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 11, 2021, as Appl. No. 17/524,333.
Prior Publication US 2022/0067524 A1, Mar. 3, 2022
Int. Cl. H03M 7/00 (2006.01); G06N 3/08 (2023.01); G06N 5/04 (2023.01); H03M 7/30 (2006.01)
CPC G06N 3/08 (2013.01) [G06N 5/04 (2013.01); H03M 7/6005 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A computing system comprising:
a plurality of processing elements;
a memory to store compressed data associated with a plurality of tensors and a sparsity bitmap, wherein the compressed data is to be in a compressed format; and
a decode buffer that includes logic implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
prefetch the compressed data from the memory;
align the compressed data with the sparsity bitmap to generate decoded data; and
provide the decoded data to the plurality of processing elements.