US 12,229,661 B2
Arithmetic device and electronic device
Takahiko Ishizu, Sagamihara (JP); Takayuki Ikeda, Atsugi (JP); Atsuo Isobe, Isehara (JP); Atsushi Miyaguchi, Hadano (JP); and Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Nov. 16, 2023, as Appl. No. 18/510,784.
Application 18/510,784 is a continuation of application No. 17/588,613, filed on Jan. 31, 2022, granted, now 11,868,877.
Application 17/588,613 is a continuation of application No. 16/641,821, granted, now 11,275,993, issued on Mar. 15, 2022, previously published as PCT/IB2018/056531, filed on Aug. 28, 2018.
Claims priority of application No. 2017-171509 (JP), filed on Sep. 6, 2017; application No. 2017-171511 (JP), filed on Sep. 6, 2017; and application No. 2017-171524 (JP), filed on Sep. 6, 2017.
Prior Publication US 2024/0095507 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/065 (2023.01); G06F 1/3234 (2019.01); G06F 7/544 (2006.01); G06T 1/20 (2006.01)
CPC G06N 3/065 (2023.01) [G06F 1/3243 (2013.01); G06F 7/5443 (2013.01); G06T 1/20 (2013.01)] 5 Claims
OG exemplary drawing
 
1. An arithmetic device comprising:
a first arithmetic portion; and
a second arithmetic portion,
wherein the first arithmetic portion comprises a first central processing unit (CPU) core and a second CPU core,
wherein the second arithmetic portion comprises a first graphics processing unit (GPU) core and a second GPU core,
wherein the first CPU core and the second CPU core each are configured to perform power gating,
wherein the first CPU core and the second CPU core each comprise a first data retention circuit,
wherein the first GPU core comprises a second data retention circuit configured to retain an analog value and read out the analog value as digital data of two or more bits,
wherein the second GPU core comprises a third data retention circuit configured to retain a digital value and read out the digital value as digital data of one bit,
wherein the first to third data retention circuits each comprise a first transistor, a second transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor, and
wherein a channel formation region of the first transistor comprises an oxide semiconductor.