US 12,229,658 B2
Configurable processor for implementing convolution neural networks
Pavel Sinha, Brossard (CA)
Assigned to AARISH TECHNOLOGIES, Brossard (CA)
Filed by Pavel Sinha, Brossard (CA)
Filed on Jul. 20, 2020, as Appl. No. 16/933,859.
Claims priority of provisional application 63/025,580, filed on May 15, 2020.
Claims priority of provisional application 62/941,646, filed on Nov. 27, 2019.
Claims priority of provisional application 62/876,219, filed on Jul. 19, 2019.
Prior Publication US 2021/0034958 A1, Feb. 4, 2021
Int. Cl. G06N 3/063 (2023.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G06N 3/08 (2013.01)] 39 Claims
OG exemplary drawing
 
1. A configurable processor dedicated to implementing convolution neural networks (CNNs) and implemented in a single integrated circuit die, comprising:
a plurality of core compute circuits on the die, each configured to perform a CNN function in accordance with a preselected dataflow graph;
an active memory buffer on the die;
a plurality of connections, on the die, between the active memory buffer and the plurality of core compute circuits, each established in accordance with the preselected dataflow graph; and
a plurality of connections, on the die, between the plurality of core compute circuits, each established in accordance with the preselected dataflow graph,
wherein the active memory buffer on the die is configured to store data from, and move data between, the plurality of core compute circuits in accordance with the preselected dataflow graph,
wherein each of the plurality of core compute circuits is configured to perform the CNN function in accordance with the preselected dataflow graph and without using an instruction set, and
wherein the active memory buffer is further configured to apply backpressure on a data generation source.