US 12,229,657 B2
Multi-mode planar engine for neural processor
Christopher L. Mills, Saratoga, CA (US); Kenneth W. Waters, San Jose, CA (US); and Youchang Kim, Cupertino, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Oct. 8, 2019, as Appl. No. 16/596,439.
Prior Publication US 2021/0103803 A1, Apr. 8, 2021
Int. Cl. G06N 3/063 (2023.01); G06F 17/15 (2006.01); G06N 20/00 (2019.01)
CPC G06N 3/063 (2013.01) [G06F 17/15 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A neural processor, comprising:
a plurality of neural engine circuits, each of the plurality of neural engine circuits configured to perform a convolution operation of first input data with one or more kernels to generate a first output; and
a planar engine circuit coupled to the plurality of neural engine circuits and configured to operate in parallel with the plurality of neural engine circuits, the planar engine circuit operable in one of two or more modes that include a pooling mode and an elementwise mode to generate a second output, the planar engine circuit comprising a programmable line buffer circuit, wherein the programmable line buffer circuit is configured to store intermediate results generated by the planar engine circuit in the pooling mode, wherein the planar engine circuit is configured to bypass storage of results, in the programmable line buffer circuit, generated by the planar engine circuit in the elementwise mode, and wherein:
in the pooling mode, the planar engine circuit is configured to reduce a spatial size of a version of second input data received by the planar engine circuit, the second input data corresponding to the first output or a version of input data of the neural processor, and
in the elementwise mode, the planar engine circuit is configured to perform an elementwise operation on the second input data, the second input data corresponding to the first output or a version of the input data of the neural processor; and
a data processor circuit coupled to the plurality of neural engine circuits and to the planar engine circuit, the data processor circuit configured to buffer the second output for sending to the plurality of neural engine circuits.