US 12,229,568 B2
Methods and circuitry for efficient management of local branch history registers
Rami Mohammad Al Sheikh, Morrisville, NC (US); Ahmed Helmi Mahmoud Osman Abulila, Raleigh, NC (US); Daren Eugene Streett, Cary, NC (US); and Michael Scott McIlvaine, Raleigh, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Aug. 4, 2023, as Appl. No. 18/365,418.
Application 18/365,418 is a continuation of application No. 17/831,116, filed on Jun. 2, 2022, granted, now 11,768,688.
Prior Publication US 2023/0393854 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3861 (2013.01) [G06F 9/30101 (2013.01); G06F 9/3804 (2013.01); G06F 9/3844 (2013.01); G06F 9/3806 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for managing local branch history registers of a processor including a pipeline comprising a plurality of stages, the method comprising:
providing a bit-vector associated with each of in-flight branches associated with the pipeline, wherein each bit-vector having a bit corresponding to each local branch history register associated with a respective in-flight branch;
providing a recovery counter associated with each local branch history register for tracking a number of bits needing recovery before a local branch history register is valid for participation in branch prediction;
in response to an update of a local branch history register by a branch, setting a bit in a corresponding bit-vector indicative of the update of the local branch history register by the branch; and
upon a flush, determining a value indicative of an extent of recovery required for each local branch history register affected by the flush, and setting a corresponding recovery counter to the value indicative of the extent of recovery required.