| CPC G06F 9/30076 (2013.01) [G06F 9/3836 (2013.01); G06F 11/30 (2013.01)] | 21 Claims |
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1. A processor comprising:
an interconnect;
a memory controller coupled to the interconnect; and
a plurality of cores coupled to the interconnect, a core of the plurality of cores comprising:
an instruction cache to store instructions,
an instruction translation lookaside buffer (ITLB) to store virtual-to-physical address translations associated with the instructions,
instruction fetch circuitry to fetch the instructions,
decode circuitry to decode the instructions,
fetch sampling circuitry to track multiple types of events corresponding to the instructions fetched by the instruction fetch circuitry, the fetch sampling circuitry comprising:
at least one model specific register (MSR) to be programmed with values to indicate the types of events to be tracked, the types of events including instruction cache miss events, ITLB miss events, L3 cache miss events, and decoded micro-op cache miss events, and
filtering circuitry configurable to limit tracking or reporting to a subset of the types of events based on a filtering indication, and
circuitry to generate interrupts to report events associated with the subset.
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