CPC G06F 9/30043 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30087 (2013.01); G06F 9/321 (2013.01); G06F 9/3826 (2013.01); G06F 9/3834 (2013.01); G06F 9/3842 (2013.01); G06F 9/528 (2013.01); G06F 2209/521 (2013.01)] | 20 Claims |
1. A processor, comprising:
a load/store unit configured to execute atomic operations;
a predictor circuit configured to generate a prediction of whether an atomic operation executed by the load/store unit will complete successfully, wherein the atomic operation specifies a load operation from a memory location, a data operation on first data from the load operation, and a store operation to write second data to the memory location, wherein the store operation is conditional on a result of the data operation, and wherein the atomic operation is defined to complete unsuccessfully based on the store operation not being performed; and
one or more pipeline circuits configured to reduce power consumption based on the prediction indicating that the atomic operation will complete unsuccessfully.
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