US 12,229,557 B2
Atomic operation predictor to predict whether an atomic operation will complete successfully
Brian R. Mestan, Austin, TX (US); Gideon N. Levinsky, Cedar Park, TX (US); and Michael L. Karm, Cedar Park, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 11, 2024, as Appl. No. 18/601,640.
Application 18/601,640 is a continuation of application No. 17/473,076, filed on Sep. 13, 2021, granted, now 11,928,467.
Application 17/473,076 is a continuation of application No. 16/906,396, filed on Jun. 19, 2020, granted, now 11,119,767, issued on Sep. 14, 2021.
Prior Publication US 2024/0248717 A1, Jul. 25, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/52 (2006.01)
CPC G06F 9/30043 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30087 (2013.01); G06F 9/321 (2013.01); G06F 9/3826 (2013.01); G06F 9/3834 (2013.01); G06F 9/3842 (2013.01); G06F 9/528 (2013.01); G06F 2209/521 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor, comprising:
a load/store unit configured to execute atomic operations;
a predictor circuit configured to generate a prediction of whether an atomic operation executed by the load/store unit will complete successfully, wherein the atomic operation specifies a load operation from a memory location, a data operation on first data from the load operation, and a store operation to write second data to the memory location, wherein the store operation is conditional on a result of the data operation, and wherein the atomic operation is defined to complete unsuccessfully based on the store operation not being performed; and
one or more pipeline circuits configured to reduce power consumption based on the prediction indicating that the atomic operation will complete unsuccessfully.