US 12,229,484 B1
Timing path analysis using flow graphs
Oliver Kozber, Beaverton, OR (US); and Colin Williams, Cary, NC (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Nov. 24, 2021, as Appl. No. 17/535,040.
Claims priority of provisional application 63/117,703, filed on Nov. 24, 2020.
Int. Cl. G06F 30/3312 (2020.01); G06F 3/04842 (2022.01); G06F 30/31 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 3/04842 (2013.01); G06F 30/31 (2020.01); G06F 2119/12 (2020.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
receiving timing data associated with an integrated circuit (IC) design, wherein the timing data includes a plurality of timing paths;
generating, by a processor, a graphical representation of the plurality of timing paths as a plurality of corresponding flow ribbons, wherein a timing path of the plurality of timing paths is represented as a flow ribbon of the plurality of corresponding flow ribbons across one or more components of the IC design and wherein a display attribute of the flow ribbon is indicative of a metric of the timing path; and
providing the graphical representation in a graphical user interface (GUI) to a user.