| CPC G06F 30/323 (2020.01) [G03F 1/70 (2013.01); G06F 30/3323 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2119/12 (2020.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, the method comprising:
migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including:
generating first versions correspondingly of the first and second netlists;
abstracting selected components in the first version of the second netlist and correspondingly in the first version of the first netlist to form corresponding second versions of the second and first netlists;
performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and
revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.
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