US 12,229,451 B2
Truth table extension for stacked memory systems
Joseph T. Pawlowski, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 13, 2024, as Appl. No. 18/604,050.
Application 18/604,050 is a continuation of application No. 18/099,051, filed on Jan. 19, 2023, granted, now 11,934,705.
Application 18/099,051 is a continuation of application No. 17/127,785, filed on Dec. 18, 2020, granted, now 11,561,731.
Claims priority of provisional application 62/953,819, filed on Dec. 26, 2019.
Prior Publication US 2024/0220163 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage system comprising:
a stack of first memory die;
a logic die having a second memory with relatively faster access time than the first memory die;
an interface circuit configured to receive memory requests using a first command bus and a second command bus; and
a controller configured to:
directly access the second memory based on commands on both the first and second command busses; and
select between a buffer of the logic die or a data bus as a data target for data accessed from the second memory, wherein the selection is based on a state of a particular bit in the command on the second command bus.