US 12,229,447 B2
Nonvolatile semiconductor memory
Hiroshi Maejima, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 6, 2023, as Appl. No. 18/242,521.
Application 18/242,521 is a continuation of application No. 17/494,015, filed on Oct. 5, 2021, granted, now 11,789,656.
Application 17/494,015 is a continuation of application No. 16/804,037, filed on Feb. 28, 2020, granted, now 11,169,742, issued on Nov. 9, 2021.
Claims priority of application No. 2019-113565 (JP), filed on Jun. 19, 2019.
Prior Publication US 2023/0409241 A1, Dec. 21, 2023
Int. Cl. G06F 3/06 (2006.01); G06N 3/08 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06N 3/08 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory comprising:
a plurality of memory cells;
a plurality of bit lines connected to the plurality of memory cells;
a first circuit configured to control the plurality of bit lines according to first data;
a source line commonly connected to first ends of the plurality of bit lines; and
a second circuit connected to the source line and configured to detect second data according to a current amount in the source line,
wherein:
the second circuit includes a third circuit and a fourth circuit,
the third circuit is configured to compare a first voltage with a second voltage, the first voltage being a reference voltage, and the second voltage being a voltage of the source line based on the current amount in the source line, and
the fourth circuit is configured to digitally convert the current amount in the source line.