| CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 7/582 (2013.01)] | 11 Claims |
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1. A memory system connectable to a host device, the memory system comprising:
a nonvolatile memory;
a first circuit configured to generate a sequence of random number bits; and
a processor configured to:
instruct the first circuit to generate a sequence of random number bits having a first length,
calculate a first value indicating randomness of the sequence of random number bits,
determine whether the first value exceeds a first threshold value,
upon determining that the first value does not exceed the first threshold value, notify the host device of an error, and
upon determining that the first value exceeds the first threshold value,
determine whether the first value exceeds a second threshold value that is greater than the first threshold value, and
upon determining that the first value exceeds the second threshold value,
generate a first pseudo random number using the sequence of random number bits, and
write data to the nonvolatile memory using the first pseudo random number, and
upon determining that the first value does not exceed the second threshold value,
update the second threshold value to a third threshold value that is less than the second threshold value and greater than the first threshold value, and then determine a second length corresponding to the third threshold value, the second length being greater than the first length,
instruct the first circuit to generate another sequence of random number bits having the second length,
generate a second pseudo random number using said another sequence of random number bits, and
write data to the nonvolatile memory using the second pseudo random number.
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